YAN LIN
Campus Address
53-135W Engineering IV, UCLA
Home Address
3210 Sawtelle Blvd. APT 105 Los Angeles, CA 90066 Email: ylin@ee.ucla.edu
Los Angeles, CA 90095 Phone: 310-267-5407 (O)
310-309-9629 (M)
OBJECTIVE
Full time position in 2007 on design automation, FPGA or structured ASIC
EDUCATION
University of California, Los Angeles March 2003 – Present
Ph.D. program, Electrical Engineering March 2003 – June 2004 M.Sc. in Electrical Engineering (GPA: 3.8/4.0) n Related course project:
o Designed a single-ported 256x Content Addressable Memory (CAM) o A High /Low-pass/Gain digital filter micro-architecture and circuit design o Simulated annealing based configurable sensor network deployment o Detailed placement for standard cell based placement Tsinghua University, P.R.China Sep 1998 – Jun 2002 B.S. in Department of Automation (GPA:88/100 Rank: 5/160)
PROFESSIONAL EXPERIENCE
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March 2003 – present, Graduate Student Research Assistant, UCLA Design Automation Lab June 2006 – Sept. 2006, Intern Research Engineer, Software Department, Altera Corp., San Jose, CA o Developed various tools integrated in Quartus II for next generation FPGA
architecture research July 2005 – Dec. 2005, Intern Research Engineer, Software Department, Altera Corp., San Jose, CA o Evaluated various academic logic synthesis and technology mapping
algorithms compared to Altera Quartus II using MCNC and QUIP designs. o Analyzed statistical timing considering guard-banding and speed-binning
with process variations and developed a novel stochastic placement algorithm with 25X yield loss reduction March 2004 – June 2004, Teaching Assistant, “EE M16: Digital Logic Design”, Electrical Engineering Department, University of California, Los Angeles
RESEARCH
“Novel Circuit and Fabric Design for Power Efficient FPGAs and related CAD” UCLA Design Automation Lab
n Designed low-power FPGA circuits and architectures using pre-determined/
configurable dual-Vdd/Vt technique and related CAD development
Developed timing slack allocation algorithms for Vdd-programmable interconnects without using Vdd-level converter for power maximization
n Performed FPGA architecture evaluation considering Vdd programmability and
simultaneous device and architecture co-optimization “Process Variation Modeling and Variation-Aware Physical Synthesis for FPGA” n Developed closed-form timing and power models with process variations and
performed FPGA architecture and device co-optimization considering variations n Process variation extraction and modeling, stochastic physical synthesis, e.g.
clustering, placement, routing, retiming and the interaction between them
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PUBLICATIONS
Journal articles
n Yan Lin, Fei Li and Lei He, “Circuits and Architecture Evaluation for Field
Programmable Gate Array with Configurable Supply Voltage”, IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 13, No. 9, Sept. 2005, pp. 1035-1047
n Fei Li, Yan Lin, Lei He, Deming Cheng and Jason Cong, “Power modeling and
characteristics of field programmable gate arrays”, IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems, Vol. 24, No. 11, Nov. 2005, pp. 1712-1724 n Yan Lin and Lei He, “Dual-Vdd Interconnect with Chip Level Time Slack
Allocation for FPGA Power Reduction”, IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems, Vol. 25, No. 10, Oct. 2006, pp. 2023-2034
n Fei Li, Yan Lin and Lei He, “Field Programmability of Supply Voltage for FPGA
Power Reduction”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems
n Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong and Lei He, \"Device and
Architecture Co-optimization for FPGA Power Reduction\accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems n Yan Lin, Lei He and Mike Hutton, “Stochastic Physical Synthesis Considering
Pre-routing Interconnect Uncertainty and Process Variation for FPGAs”, submitted to IEEE Transactions on Very Large Scale Integration (VLSI) Systems
n Lerong Cheng, Yan Lin, Phoebe Wong and Lei He, “FPGA Device and
Architecture Evaluation Considering Process Variations”, submitted to IEEE Transactions on Very Large Scale Integration (VLSI) Systems n Yu Hu, Yan Lin, Lei He and Tim Tuan, “Physical Synthesis for FPGA
Interconnect Power Reduction by Dual-Vdd Budgeting and Retiming, submitted to ACM Transactions on Design Automation of Electronic Systems (TODAES) Conference papers
n Fei Li, Yan Lin, Lei He and Jason Cong, “Low-Power FPGA using Pre-Defined
Dual-Vdd/Dual-Vt Fabrics”, FPGA Symposium, pp. 42-50, Feb 2004 n Fei Li, Yan Lin and Lei He, “FPGA Power Reduction Using Configurable
Dual-Vdd”, Design Automation Conference, pp. 735-740, June 2004
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Fei Li, Yan Lin and Lei He, “Vdd Programmability to Reduce FPGA Interconnect Power”, International Conference on Computer Aided Design, pp. 760-765, Nov 2004
Yan Lin, Fei Li and Lei He, “Routing Track Duplication with Fine-Grained Power-Gating for FPGA Interconnect Power Reduction”, Asia South Pacific Design Automation Conference, pp. 5-650, January 2005 Yan Lin, Fei Li and Lei He, “Power Modeling and Architecture Evaluation for FPGA with Novel Circuits for Vdd Programmability”, FPGA Symposium, pp. 199-207, Feb 2005 Yan Lin and Lei He, “Leakage Efficient Chip-level Dual-Vdd Assignment with Time Slack Allocation for FPGA Power Reduction”, Design Automation Conference, pp. 720-725, June 2005
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin and Lei He, “Device and Architecture Co-optimization for FPGA Power Reduction”, Design Automation Conference, pp. 915-920, June 2005
Phoebe Wong, Lerong Cheng, Yan Lin and Lei He, “FPGA Device and Architecture Evaluation Considering Process Variation”, International Conference on Computer Aided Design, pp. 19-24, Nov 2005 Yu Hu, Yan Lin, Lei He and Tim Tuan, “Simultaneous Time Slack Budgeting and Retiming for Dual-Vdd FPGA Power Reduction”, Design Automation Conference, pp. 478-483, July 2006
Yan Lin, Mike Hutton and Lei He, “Placement and Timing for FPGA considering Variations”, International Conference on Field Programmable Logic and Applications, August 2006
Yan Lin, Yu Hu, Lei He and Vijay Raghanathan, \"An Efficient Chip-level Time Slack Allocation Algorithm for Dual-Vdd FPGA Power Reduction \International Symposium on Low Power Electronics and Design, October 2006 Proficient in C/C++
Familiar with Verilog, SpecC, MIPS, 80x86 assembly, Matlab, Perl
Familiar with Synopsys, Cadence, VPR, HSPICE, FPGAeva-LP2, Quartus II Familiar with UNIX/LINUX/WIN-NT
COMPUTER SKILLS
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PERSONAL DATA
Chinese/Male/Birth date: Dec. 28th, 1980
Prof. Lei He, Department of Electrical Engineering, UCLA lhe@ee.ucla.edu, (310) 206-2037
Dr. Mike Hutton, Software Department, Altera Corp., San Jose CA mhutton@altera.com, (408) 544-8253
Prof. Jason Cong, Department of Computer Science, UCLA cong@cs.ucla.edu, (310) 206-2775
Prof. Mani Srivastava, Department of Electrical Engineering, UCLA mbs@ee.ucla.edu, (310) 267-2098
REFERENCES
