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专利名称：Use of models in integrated circuit
fabrication
发明人：Taber H. Smith,Vikas Mehrotra,David White申请号：US11142606申请日：20050531
公开号：US20050235246A1公开日：20051020
专利附图：
摘要：A method and system are described to reduce process variation as a result ofthe electrochemical deposition (ECD), also referred to as electrochemical plating (ECP),and chemical mechanical polishing (CMP) processing of films in integrated circuit
manufacturing processes. The described methods use process variation and electricalimpact to direct the insertion of dummy fill into an integrated circuit.
申请人：Taber H. Smith,Vikas Mehrotra,David White
地址：Fremont CA US,Fremont CA US,Cambridge MA US
国籍：US,US,US
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