Verilog HDL数字系统设计及仿真实验报告
实验名称:十字路口交通信号灯
实验日期: 2016.5.24
专业班级:14电子科学与技术 姓名: 彭小标 指导教师:黄秋萍
一、实验目的
编写一个十字路口交通信号灯使得满足下列表格:
东西 黄灯y2 绿灯g2 红灯r2 5s 45s 60s 黄灯y1 绿灯g1 5s 55s 红灯r1 南北 50s 二、实验内容
1.没有计数器的十字路口红绿灯 ○
代码为:
module trafficlight1(clk,reset,r1,y1,g1,r2,y2,g2); input clk,reset;
output r1,y1,g1,r2,y2,g2; reg r1,y1,g1,r2,y2,g2;
reg [1:0]cs,ns;
parameter r1s=3'b000, y1s=3'b001, g1s=3'b010, r2s=3'b011, y2s=3'b100, g2s=3'b101,
delay_r12y1=4'd50, delay_y12g1=4'd5, delay_g12r1=4'd55; always@(posedge clk,posedge reset) begin if(reset)
cs<=r1s;
else cs<=ns; end
always@(cs) begin case(cs) r1s:begin
r1=1;y1=0;g1=0;r2=0;y2=1;g2=0; #5 y2=0;g2=1;
repeat(delay_r12y1)@(posedge clk); ns=y1s; end y1s:begin
r1=0;y1=1;g1=0;r2=1;y2=0;g2=0; repeat(delay_y12g1)@(posedge clk); ns=g1s; end g1s:begin
r1=0;y1=0;g1=1;r2=1;y2=0;g2=0; repeat(delay_g12r1)@(posedge clk); ns=r1s; end default:begin
r1=1;y1=0;g1=0;ns=r1s; end endcase end endmodule 测试 module test;
reg clk,reset; wire r1,y1,g1,r2,y2,g2; initial clk=0;
always#10 clk=~clk; initial begin reset=1; #1 reset=0; #1000 reset=1; #2000 $stop; end
trafficlight1 light1(clk,reset,r1,y1,g1,r2,y2,g2); endmodule 仿真波形为:
2有计数器的十字路口红绿灯:红灯60s,黄灯5s,绿灯55s ○代码
module trafficlight2(clk,reset,r1,y1,g1,r2,y2,g2,cs,ns,lightc,lightd); input clk,reset;
output r1,y1,g1,r2,y2,g2,cs,ns,lightc,lightd; reg r1,y1,g1,r2,y2,g2; reg[1:0] cs,ns; reg [5:0] lightc,lightd;
parameter r1s=3'b000, y1s=3'b001, g1s=3'b010,
r2s=3'b011,y2s=3'b100,g2s=3'b101,
r1d=6'd50, y1d=6'd5, g1d=6'd55;
always@(posedge clk,posedge reset) begin
if(reset) lightc<=0;
else if (lightc==lightd) lightc<=1; else
lightc<=lightc+1; end
always@(posedge clk,posedge reset) begin if(reset) cs<=r1s; else cs<=ns; end
always@(cs,lightc) begin case (cs) r1s:begin
r1=1;y1=0;g1=0; r2=0;y2=1;g2=0; lightd=r1d; if(lightc==lightd) ns=y1s; end y1s:begin
r1=0; y1=1; g1=0; r2=1;y2=0;g2=0; lightd=y1d; if(lightc==lightd) ns=g1s;
end g1s:begin
r1=0;y1=0;g1=1; r2=1;y2=0;g2=0; lightd=g1d; if(lightc==lightd) ns=r1s; end default:begin r1=1; y1=0; g1=0; ns=r1s; end endcase end endmodule 仿真 module test2; reg clk,reset; wire r1,y1,g1,r2,y2,g2; wire [1:0]cs,ns; wire [5:0]lightc,lightd; initial clk=0; always#10 clk=~clk; initial begin reset=1; #1 reset=0; #10000 reset=1;
#2000 $stop; end
trafficlight2 light2(clk,reset,r1,y1,g1,r2,y2,g2,cs,ns,lightc,lightd); endmodule 输出的波形为:
上图放大显示为:
三、实验结论
时序逻辑状态设计能完成时钟控制下多种状态的变化。用有限状态机的设计能够完成交通信号红绿灯的编写。