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专利名称：Synchronizer circuit with asynchronous
clearing
发明人：Dennis E. Gates,Bret S. Weber申请号：US07/100499申请日：19870924公开号：US05012127A公开日：19910430
摘要：The present circuit incorporates a latch which latches an asynchronous inputsignal and provides a latched output signal to the first stage of a two stage synchronizer.An AND gate receives the latched output signal and the output from the first stage suchthat the output signal from the AND gate follows the output of the first synchronizerand is presented as an input to a second stage of the two stage synchronizer. The secondstage is clocked, as is the first stage, with the system clock signal to provide the
synchronized output signal. An asynchronous reset of the latch causes the output of theAND gate to go low which in turn causes the output of the second stage to go lowasynchronously.
申请人：NCR CORPORATION
代理人：Wilbert Hawk, Jr.,Stephen F. Jewett,Edward Dugas
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