HD74LS161AP资料

HD74LS161A

Synchronous 4-bit Binary Counter (direct clear)

REJ03D0445–0200

Rev.2.00 Feb.18.2005

This synchronous 4-bit binary counter features an internal carry look-ahead for application in high-speed counting

designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes coincident with each other when so instructed by the count-enable inputs and internal gating. This mode is operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A

buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This counter is fully programmable; that is, the output may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input should be avoided when the clock is low if the enable inputs are high at or before the transition. The clear function is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional getting. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produced a high-level output pulse with a duration approximately equal to the high-level

portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low-level transitions at the enable P or T inputs should occur only when the clock input is high.

Features

• Ordering Information

Part Name

Package Type

Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) PRSP0016DG-A (FP-16DNV)

Package

Abbreviation

Taping Abbreviation (Quantity)

HD74LS161AP DILP-16 pin HD74LS161AFPEL HD74LS161ARPEL

SOP-16 pin (JEITA) SOP-16 pin (JEDEC)

P — FP RP

EL (2,000 pcs/reel) EL (2,500 pcs/reel)

Note: Please consult the sales office for the above package availability.

Rev.2.00, Feb.18.2005, page 1 of 10

元器件交易网www.cecb2b.com

HD74LS161A

Pin Arrangement

ClearClockADataInputsBCDEnable PGND12345678CLRCKRippleCarryABCDPLoadQAQBQCQDT161514131211109VCCRippleCarry OutputQAQBOutputsQCQDEnable TLoad(Top view)

Block Diagram

ClockClearLoadDCKQCLRQOutputQAEnablePTADCKBQOutputQBQCLRDataInputsCDQCKQCLROutputQCDDQCKQCLROutputQDRippleCarryOutput Rev.2.00, Feb.18.2005, page 2 of 10

元器件交易网www.cecb2b.com

HD74LS161A

Absolute Maximum Ratings

Supply voltage Input voltage Power dissipation Storage temperature

VCC VIN PT Tstg

Item Symbol Ratings Unit 7 V 400 mW –65 to +150

°C

7 V Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.

Recommended Operating Conditions

Supply voltage Output current Operating temperature Clock frequency Clock pulse width Clear pulse width

A, B, C, D

Setup time Hold time

Enable P, T Load

tsu VCC IOH IOL Topr

4.75 5.00 5.25 V — — –400 µA

— — 8 mA –20 25 75 °C

ns ns ns ns

Item Symbol Min Typ Max Unit ƒclock 0 — 25 MHz tw (clock) 25 — — tw (clear) 20 — — 20 20

— —

— —

20 — — ns th 3 — — ns Typical Clear, Preset, and Inhibit Sequence

ClearLoadADataInputsBCDClockEnable PEnable TQAOutputsQBQCQDCarry12Preset(Load)1314150Count12InhibitClear Rev.2.00, Feb.18.2005, page 3 of 10

元器件交易网www.cecb2b.com

HD74LS161A

Electrical Characteristics

(Ta = –20 to +75 °C)

Item Symbol min. typ.* max. Unit Condition VIH 2.0 — — V

Input voltage

VIL — — 0.8 V

VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, VOH 2.7 — — V IOH = –400 µA

— — 0.4 IOL = 4 mA VCC = 4.75 V, VIH = 2 V,

VOL V

— — 0.5 IOL = 8 mA VIL = 0.8 V — — 20

IIH µA VCC = 5.25 V, VI = 2.7 V — — 40

— — 20 — — –0.4

mA VCC = 5.25 V, VI = 0.4 V — — –0.8 — –0.4 — — 0.1

mA VCC = 5.25 V, VI = 7 V — — 0.2

Output voltage

Input

current

Data, Enable P

Load, Clock, Enable T Clear

Data, Enable P

Load, Clock, Enable T Clear

Data, Enable P

Load, Clock, Enable T

IIL

II

Clear

Short-circuit output current Supply current**

— — 0.1 IOS –20 — –100 mA VCC = 5.25 V ICCH — 18 31 mA VCC = 5.25 V

ICCL — 19 32 mA VCC = 5.25 V VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA

Input clamp voltage

Notes: * VCC = 5 V, Ta = 25°C ** ICCH is measured with the load input high, then again with the load input low, with all other inputs high and all

outputs open. ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open.

Switching Characteristics

(VCC = 5 V, Ta = 25°C)

Item Symbol Inputs Outputs min. typ. max. Unit Condition Maximum clock frequency ƒmax Clock QA to QD 25 32 — MHz tPLH — 20 35 ns Ripple

Clock

Carry tPHL — 18 35 ns tPLH — 13 24 ns Clock

QA to QD

(Load = “H”) — 18 27 ns tPHL CL = 15 pF,

RL = 2 kΩ Propagation delay time tPLH — 13 24 ns Clock

QA to QD

(Load = “L”) — 18 27 ns tPHL

tPLH — 9 14 ns Ripple Enable T

Carry tPHL — 9 14 ns QA to QD — 20 28 ns tPHL Clear

Rev.2.00, Feb.18.2005, page 4 of 10

元器件交易网www.cecb2b.com

HD74LS161A

Timing Method

tw (CK)3VClock1.3VtsuLoad1.3VtsuDataOutputsA to D1.3Vth1.3VtsuEnableP or T1.3V1.3Vth1.3Vth3V1.3V0V3V0V3V0V 1.3V0V

Testing Method

Test Circuit

VCC4.5VRLQACLLoad circuit 1QALoadCKInputABCDSee Testing TableP.G.Zout = 50ΩQBQBQCQCQDRippleCarrySame as Load Circuit 1.Same as Load Circuit 1.Same as Load Circuit 1.InputP.G.Zout = 50ΩPTQDRippleCarryCLRSame as Load Circuit 1. Notes: 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H).

Rev.2.00, Feb.18.2005, page 5 of 10

元器件交易网www.cecb2b.com

HD74LS161A Testing Table

Item ƒmax CKRipply → Carry CK → Q CK → Q Enable Ripple

→

T Carry CLR → Q

From input to

output

Inputs

Enable Data Clear Load Clock

P T A B C D 4.5V 4.5V 4.5V 4.5V IN GND GND GND GND 4.5V 4.5V 4.5V 4.5V IN GND GND GND GND 4.5V 4.5V 4.5V 4.5V IN GND GND GND GND 4.5V GND GND GND IN IN* IN* IN* IN* 4.5V GND 4.5V IN IN

GND

GND

GND

IN* IN*

4.5V 4.5V 4.5V 4.5V 4.5V 4.5V 4.5V 4.5V tPLH

tPHL

Notes: *. For initialized Item

From input to output

Outputs

QA

QB

QC

QD Ripple Carry ƒmax OUT OUT OUT OUT OUT CK→Ripple Carry — — — — OUT CK→Q OUT OUT OUT OUT — tPLH

CK→Q OUT OUT OUT OUT — tPHL

Enable T→Ripple Carry — — — — OUT CLR→Q

OUT OUT OUT OUT — Rev.2.00, Feb.18.2005, page 6 of 10

元器件交易网www.cecb2b.com

HD74LS161A Waveforms 1

ƒmax, tPLH, tPHL, (Clock→Q, Ripple Carry) tTLHtTHL3V1.3VtPHL(Measure at tn + 2)1.3VtPHLtPLH (Measure at tn + 2)(Measure at tn + 4)QB1.3V1.3VVOLVOHVOLtPHL(Measure attn + 16)QDtPLH (Measure at tn + 15)RippleCarry1.3V1.3VtPHL(Measure at tn + 16)VOH1.3VVOLtPLH (Measure at tn + 8)VOH1.3VVOLVOLVOH1.3V0VVOHClock10%90%90%1.3V1.3V10%(Measure attn + 1)1.3Vtw (CK)tPLHQAtPLH (Measure at tn + 4)tPHL(Measure at tn + 8)QC1.3V1.3V Note: Clock input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle 50% and : ƒmax tTLH = tTHL ≤ 2.5 ns. tn is reference bit time when all outputs are low.

Rev.2.00, Feb.18.2005, page 7 of 10

元器件交易网www.cecb2b.com

HD74LS161A Waveforms 2 tPLH, tPHL, (Clock→Q) tTLH90%Clock10%tTLHtTHL90%1.3V10%tTHL90%Data InputsA, B, C or D10%tPLHOutputsQA, QB, QC or QD90%10%tPHLVOH1.3V1.3VVOL3V1.3V0V3V0V Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, Clock input: PRR = 1 MHz, duty cycle 50%, Data input: PRR = 500 kHz, duty cycle 50%

Waveforms 3

tPLH, tPHL, (Enable T→Ripple Carry) tTLH90 %1.3 VtPLHtTHL90 %1.3 V3 V10 %tPHL0 VEnable T10 %VOHCarryOutput1.3 V1.3 VVOH Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz

Waveforms 4 tPHL, (Clear→Q) tTHLClear90%1.3VtTLH90%1.3Vtw (CLR) ≥ 20nsQA to QD1.3VtPHLVOL3V10%10%0VVOH Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns Rev.2.00, Feb.18.2005, page 8 of 10

元器件交易网www.cecb2b.com

HD74LS161A

Package Dimensions

JEITA Package CodeP-DIP16-6.3x19.2-2.54RENESAS CodePRDP0016AE-BPrevious CodeDP-16FVMASS[Typ.]1.05gD16910.b 38ZEAReferenceSymbolDimension in MillimetersMinNom7.6219.26.320.327.45.060.510.400.481.300.190°2.292.540.250.3115°2.791.122.540.56MaxA 1eDEAL1A1eb pbp3θe1cbcθeZ( Ni/Pd/Au plating )L

JEITA Package CodeP-SOP16-5.5x10.06-1.27RENESAS CodePRSP0016DH-BPrevious CodeFP-16DAVMASS[Typ.]0.24g*1D9F16NOTE)1. DIMENSIONS\"*1 (Nom)\"AND\"*2\"DO NOT INCLUDE MOLD FLASH.2. DIMENSION\"*3\"DOES NOTINCLUDE TRIM OFFSET.bpHEEIndex markReferenceSymbol*2cDimension in MillimetersMinNom10.065.50Max10.5Terminal cross section ( Ni/Pd/Au plating )1Ze*3DEA28b pxML1A1Abpb1c0.000.100.202.200.340.400.460.1510.200.25AcθHE0°7.507.801.278°8.00θA 1yLexy0.120.150.800.501Detail FZLL0.701.150.90

Rev.2.00, Feb.18.2005, page 9 of 10

元器件交易网www.cecb2b.com

HD74LS161A

JEITA Package CodeP-SOP16-3.95x9.9-1.27RENESAS CodePRSP0016DG-APrevious CodeFP-16DNVMASS[Typ.]0.15g*1D9F16NOTE)1. DIMENSIONS\"*1 (Nom)\"AND\"*2\"DO NOT INCLUDE MOLD FLASH.2. DIMENSION\"*3\"DOES NOTINCLUDE TRIM OFFSET.bpIndex mark*2EHEcReferenceSymbolDimension in MillimetersMinNom9.903.95Max10.30Terminal cross section ( Ni/Pd/Au plating )1Ze*3DEA28b pxML1A1Abpb1cc10.100.140.251.750.340.400.460.150.200.25θHE0°5.806.101.278°6.20AθA 1Lyexy0.250.150.6350.401Detail FZLL0.601.081.27

Rev.2.00, Feb.18.2005, page 10 of 10

元器件交易网www.cecb2b.com

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan1.Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that troublemay occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits,(ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.Notes regarding these materials1.These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer'sapplication; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.2.Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.3.All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time ofpublication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It istherefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest productinformation before purchasing a product listed herein.The information described here may contain technical inaccuracies or typographical errors.Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductorhome page (http://www.renesas.com).4.When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure toevaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumesno responsibility for any damage, liability or other loss resulting from the information contained herein.5.Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human lifeis potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of aproduct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeateruse.6.The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.7.If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government andcannot be imported into a country other than the approved destination.Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.8.Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.Keep safety first in your circuit designs!RENESAS SALES OFFICESRefer to \"http://www.renesas.com/en/network\" for the latest and detailed information.http://www.renesas.comRenesas Technology America, Inc.450 Holger Way, San Jose, CA 95134-1368, U.S.ATel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe LimitedDukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd.10th Floor, No.99, Fushing North Road, Taipei, TaiwanTel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd.Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, ChinaTel: <86> (21) 72-1001, Fax: <86> (21) 15-2952 Renesas Technology Singapore Pte. Ltd.1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001

© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.

Colophon .2.0