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专利名称：Logic circuit and its forming method发明人：Shunzo Yamashita,Kazuo Yano,Yasuhiko
Sasaki
申请号：US10266773申请日：20021009公开号：US066968B2公开日：20040224
专利附图：
摘要：This application proposes a new logic circuit including the 1st selector (S) inwhich the control input S is controlled by the first input signal (IN), the input Ior Iiscontrolled by the second input signal (IN), and the output O is connected to the first
node (N), and the 3rd selector (S) in which the control input S is controlled by the firstnode (N), the input Iis controlled by the third input signal (IN), the input Iis controlled bythe first input signal (IN), and the output is connected to the first output signal (OUT).
申请人：HITACHI, LTD.
代理机构：Mattingly, Stanger & Malur, P.C.
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