Philips SemiconductorsProduct specification2-channel I2C multiplexer and interrupt controllerPCA9542FEATURESPIN CONFIGURATION•1-of-2 bi-directional translating multiplexer•Channel selection via I2C busA0114VDD•Operating supply voltage 2.5 to 3.6 VA1213SDA•Operating temperature range 0°C to 70°CA2312SCL•Power-up with all multiplexer channels deselectedINT0411INT•SD0510SC13 address pins, allowing up to 8 devices on the I2C busSC069SD1•Low on resistanceVSS78INT1DESCRIPTIONSW00475The PCA9542 is a 1-of-2 bi-directional translating multiplexer,controlled via the I2C bus. The SCL/SDA upstream pair fans out totwo SCx/SDx downstream pairs, or channels. Only one SCx/SDxchannel is selected at a time, determined by the contents of thePIN DESCRIPTIONprogrammable control register. Two interrupt inputs, one for each ofthe SCx/SDx downstream pair, are provided. One interrupt output,PINNUMBERSYMBOLFUNCTIONwhich acts as an AND of the two interrupt inputs, is provided. All I/Opins are 5 V tolerant.1A0Address input 0The pass gates of the multiplexer are constructed such that the V2A1Address input 1DDpin can be used to limit the maximum high voltage which will be3A2Address input 2passed by the PCA9542. This allows the use of different bus4INT0Interrupt input 0voltages on each SCx/SDx pair, so that 3.3 V parts cancommunicate with 5 V parts without any additional protection.5SD0Serial data 0External pull-up resistors can pull the bus up to the desired voltage6SC0Serial clock 0level for this channel.7VSSSupply ground8INT1Interrupt input 19SD1Serial data 110SC1Serial clock 111INTInterrupt output12SCLSerial clock line13SDASerial data line14VDDSupply voltageORDERING INFORMATIONPACKAGESTEMPERATURE RANGEORDER CODEDRAWING NUMBER14-Pin Plastic TSSOP0°C to +70°CPCA9542PW DHSOT402-11999 Oct 072853–2177 22486Philips SemiconductorsProduct specification2-channel I2C multiplexer and interrupt controllerPCA9542BLOCK DIAGRAMSC0SC1SD0SD1VSSVDDPOWER-ON RESETSCLA0INPUT I2C-BUSFILTERCONTROLA1SDAA2INT[0–1]INT LOGICINTSW003791999 Oct 073Philips SemiconductorsProduct specification2-channel I2C multiplexer and interrupt controllerPCA9542CHANNEL SELECTIONA SC0x/SD0x downstream pair, or channel, is selected by thecontents of the control register. This register is written after thePCA9542 has been addressed. The 3 LSBs of the control byte areused to determine which channel is to be selected. When a channelis selected, the channel will become active after a stop condition hasbeen placed on the I2C bus. This ensures that all SCx/SDx lines willbe in a HIGH state when the channel is made active, so that nofalse conditions are generated at the time of connection.CONTROL BYTESELECTED76543210CHANNELXXXXX0XXnoneXXXXX1000 (SC0/SD0)XXXXX1011 (SC1/SD1)CONTROL REGISTER 7 6 5 43 2 1 0 XX INT1 INT0 X B2 B1 B0Interrupt bitsChannel select bits(read only)(read/write)SW00477POWER-ON RESETDuring power-up, the control register defaults to all zeroes causingall the channels to be deselected.1999 Oct 074INTERRUPT HANDLINGThe PCA9542 provides 2 interrupt inputs, one for each channel andone open drain interrupt output. When an interrupt is generated by anydevice, it will be detected by the PCA9542 and the interrupt outputwill be driven LOW. The channel need not be active for detection ofthe interrupt. A bit is also set in the control byte.Bits 4 – 5 of the control byte correspond to channels 0 – 1 of thePCA9542, respectively. Therefore, if an interrupt is generated by anydevice connected to channel 1, then bit 5 will be set in the controlregister. Likewise, an interrupt on any device connected to channel 0would cause bit 4 of the control register to be set. The master canthen address the PCA9542 and read the contents of the control byteto determine which channel contains the device generating theinterrupt. The master can then reconfigure the PCA9542 to select thischannel, and locate the device generating the interrupt and clear it.It should be noted that more than one device can be providing aninterrupt on a channel, so it is up to the master to ensure that alldevices on a channel are interrogated for an interrupt.76543210INTERRUPTINGCHANNEL0001XXXX0 (SC0/SD0)0010XXXX1 (SC1/SD1)Philips SemiconductorsProduct specification2-channel I2C multiplexer and interrupt controllerPCA9542CHARACTERISTICS OF THE I2C-BUSStart and stop conditionsThe I2C-bus is for 2-way, 2-line communication between different ICsBoth data and clock lines remain HIGH when the bus is not busy. Aor modules. The two lines are a serial data line (SDA) and a serialHIGH-to-LOW transition of the data line, while the clock is HIGH isclock line (SCL). Both lines must be connected to a positive supplydefined as the start condition (S). A LOW-to-HIGH transition of thevia a pull-up resistor when connected to the output stages of a device.data line while the clock is HIGH is defined as the stop condition (P)Data transfer may be initiated only when the bus is not busy.(see Figure 2).Bit transferSystem configurationOne data bit is transferred during each clock pulse. The data on theA device generating a message is a transmitter: a device receivingSDA line must remain stable during the HIGH period of the clockis the receiver. The device that controls the message is the masterpulse as changes in the data line at this time will be interpreted asand the devices which are controlled by the master are the slavescontrol signals (see FIgure 1).(see Figure 3).SDASCL data line change stable; of datadata validallowedSW00363Figure 1. Bit transferSDASDASCLSPSCLSTART conditionSTOP conditionSW00365Figure 2. Definition of start and stop conditionsSDASCL MASTERTRANSMITTER/ SLAVE SLAVE RECEIVER RECEIVERTRANSMITTER/ MASTER MASTER I2C RECEIVERTRANSMITTERTRANSMITTER/ RECEIVERMULTIPLEXER SLAVESW00366Figure 3. System configuration1999 Oct 075Philips SemiconductorsProduct specification2-channel I2C multiplexer and interrupt controllerPCA9542AcknowledgeThe number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bitsis followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates anextra acknowledge related clock pulse.A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate anacknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull downthe SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clockpulse, set-up and hold times must be taken into account.A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out ofthe slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.DATA OUTPUT BY TRANSMITTERnot acknowledgeDATA OUTPUT BY RECEIVER acknowledge SCL FROMMASTER 12 Sclock pulse forSTART conditionacknowledgementSW00368Figure 4. Acknowledgement on the I2C-busslave address1 1 1 0A2A1 A0fixedhardware selectableSW00453Figure 5. Slave addressSDAXXXXXXXXXXXXXXXXSCL12345671234567SLAVE ADDRESSCONTROL REGISTERSDAS11 1 0 A2A1 A00A XX INT1 INT0 XB2 B1 B0APstart conditionR/Wacknowledgeacknowledgefrom slavefrom slavePREVIOUS CHANNELNEW CHANNELtpvSW00480Figure 6. WRITE control registerSLAVE ADDRESSCONTROL REGISTERlast byteSDAS1110A2 A1 A01A XX INT1 INT0 XB2 B1 B0NAPstart conditionR/Wacknowledgeno acknowledgestop conditionfrom slavefrom masterSW00481Figure 7. READ control register1999 Oct 076Philips SemiconductorsProduct specification2-channel I2C multiplexer and interrupt controllerPCA9542ABSOLUTE MAXIMUM RATINGS1, 2In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V).SYMBOLPARAMETERCONDITIONSRATINGUNITVDDDC supply voltage–0.5 to +7.0VVIDC input voltage–0.5 to +7.0VIIDC input current±20mAIODC output current±25mAIDDSupply current±100mAISSSupply current±100mAPtottotal power dissipation400mWTstgStorage temperature range–60 to +150°CTambOperating ambient temperature0 to +70°CNOTES:1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of thedevice at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure toabsolute-maximum-rated conditions for extended periods may affect device reliability.2.The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junctiontemperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.DC CHARACTERISTICSVDD = 2.5 to 3.6 V; VSS = 0 V; Tamb = 0°C to +70°C; unless otherwise specified.SYMBOLPARAMETERTESTTEST CONDITIONSCONDITIONSLIMITSMINTYPMAXUNITSupplyVDDQn ≤ VDDSupply voltage2.53.6VOperating mode; VIDDSupply currentDD = 3.6 V; no load; VI = VDD or V–20100µAfSS; SCL = 100 kHzIstbStandby currentStandby mode; Vno load; VDD = 3.6 V;I = VDD or VSS–2.5100µAVPORPower-on reset voltageVDD = 3.6 V; no load;VI = VDD or VSS–1.32.1VInput SCL; input/output SDAVILLOW level input voltage–0.5–0.3 VDDVVIHHIGH level input voltage0.7 VDD–6VIOL LOW level outLOWleveloutputut currentcurrentVOL = 0.4 V3––VOL = 0.6 V6––mAILLeakage currentVI = VDD or VSS–1–+1µACiInput capacitanceVI = VSS––10pFSelect inputs A0 to A2 / INT0 to INT3VILLOW level input voltage–0.5–+0.3 VDDVVIHHIGH level input voltage0.7 VDD–VDD + 0.5VILIInput leakage currentpin at VDD or VSS–1–+1µAPass GateR52030ONSwitchSwitch resistanceresistanceVCC = 3.67 V, VO = 0.4 V, IO = 15 mAVCC = 2.3 to 2.7 V, VO = 0.4V, IO = 10 mA72655ΩVswin = VDD = 3.3 V; Iswout = –100 µA2.2V1.62.8PassPSwitchSwitch outoutputut voltagevoltageVswin = VDD = 3.0 to 3.6 V; Iswout = –100 µAVswin = VDD = 2.5 V; Iswout = –100 µA1.5VVswin = VDD = 2.3 to 2.7 V; Iswout = –100 µA1.12.0ILLeakage currentVI = VDD or VSS–1–+1µAINT OutputIOLLOW level output currentVOL = 0.4 V3––mAILLeakage currentVI = VDD or VSS–1–+1µA1999 Oct 077Philips SemiconductorsProduct specification2-channel I2C multiplexer and interrupt controllerPCA9542AC CHARACTERISTICSSTANDARD-MODESYMBOLPARAMETERI2C-BUSFAST-MODE I2C-BUSUNITMINMAXMINMAXtpdPropagation delay from SDA to SDn or SCL to SCn0.310.31nsfSCLSCL clock frequency01000400KHztBUFBus free time between a STOP and START condition4.7–1.3–µstHD:STAHold time (repeated) START conditionAfter this period, the first clock pulse is generated4.0–0.6–µstLOWLOW period of the SCL clock4.7–1.3–µstHIGHHIGH period of the SCL clock4.0–0.6–µstSU:STASet-up time for a repeated START condition4.7–0.6µsData hold time:tHD:DATfor CBUS compatible masters5.0–––µsfor I2C-bus devices02–020.93µstSU:DATData set-up time250–1004–nstSU:STOSet-up time for STOP condition–100020 + 0.1Cb5300nstrRise time of both SDA and SCL signals–30020 + 0.1Cb5300nstfFall time of both SDA and SCL signals4.0–0.6–µsCbCapacitive load for each bus line400–400pFINTtivINTn to INT active valid time44µstirINTn to INT inactive delay time22µsLpwrLOW level pulse width rejection or INTn inputs11nsHpwrHIGH level pulse width rejection or INTn inputs500500nsNOTES:1.Pass gate propagation delay is calculated from the 20 Ω typical R2.A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHON and and the 15 pF load capacitance.the undefined region of the falling edge of SCL.min of the SCL signal) in order to bridge3.The maximum tC bus device can be used in a standard-mode IHD:DAT has only to be met if the device does not stretch the LOW period (t2C-bus system, but the requirement tLOW) of the SCL signal.4.A fast-mode I2SU:DAT ≥ 250 ns must then be met. Thiswill automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW periodof the SCL signal, it must output the next data bit to the SDA line t2rmax + tSU:DAT = 1000 + 250 = 1250 ns (according to the standard-modeIC-bus specification) before the SCL line is released.5.Cb = total capacitance of one bus line in pF.SDAtBUFtLOWtRtFtHD;STAtSPSCLtHD;STAtSU;STAtSU;STOPStHD;DATtHIGHtSU;DATSrPSU005Figure 8. Definition of timing on the I2C-bus1999 Oct 078Philips SemiconductorsProduct specification
2-channel I2C multiplexer and interrupt controller
PCA9542
TSSOP20:plastic thin shrink small outline package; 20 leads; body width 4.4 mmSOT360-1
1999 Oct 079
Philips SemiconductorsProduct specification
2-channel I2C multiplexer and interrupt controller
PCA9542
Purchase of Philips I2C components conveys a license under the Philips’ I2C patentto use the components in the I2C system provided the system conforms to theI2C specifications defined by Philips. This specification can be ordered using thecode 9398 393 40011.Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. Fordetailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above oneor more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these orat any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extendedperiods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. PhilipsSemiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing ormodification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products canreasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applicationsdo so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standardcells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes noresponsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to theseproducts, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unlessotherwise specified.
Philips Semiconductors811 East Arques AvenueP.O. Box 3409
Sunnyvale, California 94088–3409Telephone 800-234-7381
© Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Date of release: 10-99
Document order number:9397–750–096PhilipsSemiconductors1999 Oct 0710
